1. Field of the Invention
The invention relates to a method for fabricating semiconductor device, and more particularly, to a method of forming spacer enclosing void adjacent to a gate structure.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the FinFET can be controlled by adjusting the work function of the gate.
However, parasitic capacitor resulted between gate structure and contact plug has become a common problem in current FinFET fabrication process and also influenced the performance of the entire device substantially. Hence, how to improve the current process to resolve this issue has become an important task in this field.